Timing Driven Placement Algorithm for Standard-Cell Design

الموضوعات

علوم تطبيقية وتكنولوجية

الملخص

The performance of present VLSI circuits is dominated by interconnect delays. Therefore, there is a great demand to design new placement tools to incorporate performance measures of the circuits. This thesis presents a new method of solving the problem of timing driven placement for standard-cell design style using Genetic Algorithm approach. This problem is solved in an iterative manner using genetic operators. The timing problem is modeled in a path oriented manner, where timing constraints are imposed on total path delays which include both cell and interconnect delays. Improvements upto 17.7% were obtained with respect to clock speed-up of the tested examples compared to the results obtained by area driven placement tools. However, the improvements in timing have resulted in a little increase between 1.4% and 9.1% in the area of the chip after routing. The thesis work is embodied in a program called Timing Driven Genetic Algorithm for Placement (TDGAP).

روابط وملفات

التعريف والنوع

رقم الوثيقة

f24bb1d0-1d48-405c-ba70-4f49821ac585

رقم العقد

0

نوع الوسائط

Crawler

نوع المحتوى

الرسائل العلمية

صيغة المصدر

رسائل ماجيستير

نوع الملف

pdf text

أسماء الملفات

943666_1.pdf

بيانات النشر

ترجمة العنوان

خوارزمية لترتيب مواقع الخلايا المنطقية القياسية لتحسين سرعة الأداء

ألقاب المؤلفين

[{"name_ar":"Sadiq M. Sait","title_ar":"اشراف","title_en":"Supervision"},{"name_ar":"خاد محمد وليد نصار ","title_ar":"اعداد","title_en":"Preparation"}]

اللغة

English

المصدر والدورية

اسم المصدر

Timing Driven Placement Algorithm for Standard-Cell Design

المحتوى والصفحات

عدد الصفحات

0

إشراف وإعداد

الإشراف

Sadiq M. Sait

الإعداد

خاد محمد وليد نصار

الاقتباسات الببليوغرافية