Identifying Worst Case Test Vectors for FPGA Exposed to Total Ionization Dose Using Design for Testability Techniques

الموضوعات

علوم تطبيقية وتكنولوجية

الملخص

Electronic devices often operate in harsh environments which contain a variation of radiation sources. Radiation may cause different kinds of damage to proper operation of the devices. Their sources can be found in terrestrial environments, or in extra-terrestrial environments like in space, or in man-made radiation sources like nuclear reactors, biomedical devices and high energy particles physics experiments equipment. Depending on the operation environment of the device, the radiation resultant effect manifests in several forms like total ionizing dose effect (TID), or single event effects (SEEs) such as single event upset (SEU), single event gate rupture (SEGR), and single event latch up (SEL).TID effect causes an increase in the delay and the leakage current of CMOS circuits which may damage the proper operation of the integrated circuit. To ensure proper operation of these devices under radiation, thorough testing must be made especially in critical applications like space and military applications. Although the standard which describes the procedure for testing electronic devices under radiation emphasizes the use of worst case test vectors (WCTVs), they are never used in radiation testing due to the difficulty of generating these vectors for circuits under test.For decades, design for testability (DFT) has been the best choice for test engineers to test digital circuits in industry. It has become a very mature technology that can be relied on. DFT is usually used with automatic test patterns generation (ATPG) software to generate test vectors to test application specific integrated circuits (ASICs), especially with sequential circuits, against faults like stuck at faults and path delay faults. Surprisingly, however, radiation testing has not yet made use of this reliable technology. In this thesis, a novel methodology is proposed to extend the usage of DFT to generate WCTVs for delay failure in Flash based field programmable gate arrays (FPGAs) exposed to total ionizing dose (TID). The methodology is validated using Micro Semi ProASIC3 FPGA and cobalt 60 facility.

روابط وملفات

التعريف والنوع

رقم الوثيقة

eb933689-4414-4654-b331-287a86fcd311

رقم العقد

0

نوع الوسائط

Crawler

نوع المحتوى

الرسائل العلمية

صيغة المصدر

رسائل ماجيستير

نوع الملف

pdf text

أسماء الملفات

872805_1.pdf

بيانات النشر

ألقاب المؤلفين

[{"name_ar":"أحمد أبو العوف","title_ar":"اشراف","title_en":"Supervision"},{"name_ar":"محمد سامي يوسف عبدالوهاب","title_ar":"اعداد","title_en":"Preparation"}]

اللغة

English

المصدر والدورية

اسم المصدر

Identifying Worst Case Test Vectors for FPGA Exposed to Total Ionization Dose Using Design for Testability Techniques

المحتوى والصفحات

عدد الصفحات

0

إشراف وإعداد

الإشراف

أحمد أبو العوف

الإعداد

محمد سامي يوسف عبدالوهاب

الاقتباسات الببليوغرافية