An area efficient FPGA: Design using non volatile RAM

الموضوعات

علوم تطبيقية وتكنولوجية

الملخص

-The use of Field Programmable Gate Arrays (FPGAs) for the design of Application Specific Integrated Circuits (ASICs) is becoming increasingly popular. This is due to their fast turn around time, flexible architecture and their well developed design automation tools. Compared to mask Programmable Gate Arrays (MPGAs), FPGAs have the advantage of field programmability requiring only few minutes to be customized. FPGAs, however, are not a dense as MPGAs due to their programming area overhead. The architectural flexibility and gate density of FPGAs far surpasses those of the well known Electrically Programmable Logic devices (EPLDs) Several technologies have been used for FPGAs customization. These include, SRAM, anit-fuse, and floating gate technologies. In contrast to other technologies, the SRAM based FPGAs are volatile and hence the configuration data has to be loaded in the device every time the system is powered-up. Alternatively, anti-fuses are one time programmable lacking the necessary flexibility for design changes. A new floating gate technology combining the SRAM and the antifuse advantages was developed. The new technology uses a new nonvolatile SRAM cell. Compared to the standard SRAM-based FPGAs, the new technology speed increase by using a charge pump which causes a reduction of the interconnect switch resistance. Compared to antifuse-based FPGAs, the new technology is reprogrammale and fully testable. This results in high performance FPGA-implemented circuits. This work reports the initial development of an architecture based on the non volatile cell. The basic logic module was designed, laid-out and verified through simulations. The interconnect architectural parameters were studied. A model was developed to estimate such parameters.

روابط وملفات

التعريف والنوع

رقم الوثيقة

0b542cb7-138a-401b-a691-b685aceaa74c

رقم العقد

0

نوع الوسائط

Crawler

نوع المحتوى

الرسائل العلمية

صيغة المصدر

رسائل ماجيستير

نوع الملف

pdf text

أسماء الملفات

850417_1.pdf

بيانات النشر

ترجمة العنوان

تصميم مصفوفة بوابية قابلة للبرمجة باستخدام ذاكرة ثابتة مستقرة

ألقاب المؤلفين

[{"name_ar":" Alaaeldin A. M. Amin","title_ar":"اشراف","title_en":"Supervision"},{"name_ar":"Habib Youssef","title_ar":"اشراف","title_en":"Supervision"},{"name_ar":"Raffed Belal ","title_ar":"اعداد","title_en":"Preparation"}]

اللغة

English

المصدر والدورية

اسم المصدر

An area efficient FPGA: Design using non volatile RAM

المحتوى والصفحات

عدد الصفحات

0

كلمات الباحثين

Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Mask Programmable Gate Arrays (MPGAs), Electrically Programmable Logic Devices (EPLDs), SRAM technology, antifuse technology

إشراف وإعداد

الإشراف

Alaaeldin A. M. Amin, Habib Youssef

الإعداد

Raffed Belal

الاقتباسات الببليوغرافية